The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2018

Filed:

Aug. 19, 2016
Applicant:

Fairchild Korea Semiconductor Ltd., Bucheon-si, KR;

Inventors:

Kwang-won Lee, Incheon, KR;

Hye-min Kang, Goyang-si, KR;

Jae-gil Lee, Incheon, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 29/66 (2006.01); H01L 29/36 (2006.01); H01L 29/10 (2006.01); H01L 21/225 (2006.01); H01L 29/06 (2006.01); H01L 21/266 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7395 (2013.01); H01L 21/2253 (2013.01); H01L 29/0634 (2013.01); H01L 29/1095 (2013.01); H01L 29/36 (2013.01); H01L 29/66333 (2013.01); H01L 21/266 (2013.01);
Abstract

A superjunction semiconductor device includes a first semiconductor layer doped with a first conductivity type; an active region formed on the first semiconductor layer, the active region including a drift layer; and a termination region disposed to surround the active region, the termination region including a lower edge region disposed on a side surface of the drift layer and an upper edge region disposed on the lower edge region, wherein the upper edge region includes a lower charge balance region disposed on the lower edge region, the lower charge balance region having a second conductivity type different from the first conductivity type, and an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity type.


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