The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2018

Filed:

Jan. 26, 2016
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventor:

Masanori Onodera, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/56 (2006.01); H01L 23/52 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 24/48 (2013.01); H01L 25/0652 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 24/45 (2013.01); H01L 24/73 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/73203 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1052 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/19107 (2013.01);
Abstract

An example method includes disposing a semiconductor element on a first surface of a substrate. The substrate includes multiple solder balls mounted on a second surface of the substrate that is opposite to the first surface. The semiconductor element includes a bottom surface adjacent to the first surface of the substrate, a top surface, and multiple side surfaces. The example method includes forming a first molding portion to entirely enclose the multiple side surfaces and the top surface of the semiconductor element. The example method includes removing a second molding portion from the first molding portion to expose all of the top surface of the semiconductor element, leaving a third molding portion entirely enclosing the multiple sides surfaces of the semiconductor element, and coupling the semiconductor element to the first surface of the substrate by forming electrical connection between the semiconductor element and a first of the multiple solder balls.


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