The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2018

Filed:

Oct. 25, 2011
Applicants:

Stephen A. Canterbury, Antioch, IL (US);

Vernon W. Hamlin, Lisle, IL (US);

Scot W. Salzman, Buffalo Grove, IL (US);

Jorge L. Shimabukuro, Las Vegas, NV (US);

Craig J. Sylla, Round Lake, IL (US);

Inventors:

Stephen A. Canterbury, Antioch, IL (US);

Vernon W. Hamlin, Lisle, IL (US);

Scot W. Salzman, Buffalo Grove, IL (US);

Jorge L. Shimabukuro, Las Vegas, NV (US);

Craig J. Sylla, Round Lake, IL (US);

Assignee:

BALLY GAMING, INC., Las Vegas, NV (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2006.01); G06F 21/57 (2013.01); G06F 21/64 (2013.01); G07F 17/32 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4401 (2013.01); G06F 21/572 (2013.01); G06F 21/575 (2013.01); G06F 21/64 (2013.01); G07F 17/3227 (2013.01);
Abstract

In some embodiments, a wagering game machine includes: a carrier board comprising a first network port and a second network port, the first network port having a first network address and the second network port having a second network address; a processor located on the carrier board; a first nonvolatile memory located on the carrier board and communicatively coupled to the first network port, the first nonvolatile memory configured to store the first network address; and a second nonvolatile memory located on the carrier board, wherein the second nonvolatile memory is configured to store Basic Input and Output System (BIOS) code that includes a system BIOS code and an application BIOS code, wherein the BIOS code is hardware write-protected, wherein the processor is configured to derive the second network address from the first network address during execution of boot-up operations of the apparatus.


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