The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2018

Filed:

Mar. 28, 2017
Applicant:

Ningbo University, Zhejiang, CN;

Inventors:

Pengjun Wang, Zhejiang, CN;

Keji Zhou, Zhejiang, CN;

Huihong Zhang, Zhejiang, CN;

Daohui Gong, Zhejiang, CN;

Assignee:

Ningbo University, Zhejiang, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0619 (2013.01); G06F 3/065 (2013.01); G06F 3/0625 (2013.01); G06F 3/0688 (2013.01);
Abstract

The present invention discloses a replica bit-line circuit, comprising a replica unit, the 1inverter, the 2inverter, the 3inverter, the 4inverter, the 5inverter, the 6inverter, the 7inverter, the 8inverter, the 9inverter, the 1NAND gate, the 2NAND gate, the 3NAND gate, the 1NOR gate, the 2NOR gate and the 1PMOS tube; the 2NOR gate is provided with the 1input terminal, the 2input terminal, a set terminal and an output terminal; advantages of the present invention are stated as follows: It can inhibit feedback oscillation incurred by replica bit-line and replica wordline signal to obtain accurate wordline control signal; it can save switching power consumption of memory array by 53.7% under the power voltage of 1.2V.


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