The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2018

Filed:

Mar. 18, 2016
Applicant:

Genesis Photonics Inc., Tainan, TW;

Inventors:

Cheng-Wei Hung, Tainan, TW;

Yu-Feng Lin, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/38 (2010.01); H01L 33/50 (2010.01); H01L 33/56 (2010.01); H01L 33/40 (2010.01); H01L 33/00 (2010.01); H01L 27/15 (2006.01); H01L 33/52 (2010.01);
U.S. Cl.
CPC ...
H01L 33/502 (2013.01); H01L 27/156 (2013.01); H01L 33/0095 (2013.01); H01L 33/385 (2013.01); H01L 33/40 (2013.01); H01L 33/50 (2013.01); H01L 33/52 (2013.01); H01L 33/56 (2013.01); H01L 33/382 (2013.01); H01L 33/505 (2013.01); H01L 2933/005 (2013.01); H01L 2933/0016 (2013.01); H01L 2933/0041 (2013.01); H01L 2933/0066 (2013.01);
Abstract

An edge lighting light emitting diode (LED) structure and a method of manufacturing the same are provided. The edge lighting LED structure includes a substrate, an electrode pattern, a chip, an encapsulation layer and a fluorescent layer. The electrode pattern at least includes two first conducting portions separately disposed on an upper surface of the substrate, two second conducting portions separately disposed on a lower surface of the substrate, and two conducting holes separately vertically penetrating through the substrate, each conducting hole connects a first conducting portion and a second conducting portion, and the conducting holes are exposed on a lateral surface of the substrate. A second surface of the chip is disposed on the first conducting portions. A top surface of the encapsulation layer exposes and is aligned with the first surface of the chip. The fluorescent layer covers a first surface of the chip.


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