The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2018
Filed:
Jul. 11, 2016
Applicant:
Tower Semiconductor Ltd., Migdal Haemek, IL;
Inventor:
Efraim Aharoni, Haifa, IL;
Assignee:
TOWER SEMICONDUCTOR LTD., Migdal Haemek, IL;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); H01L 27/0266 (2013.01); H01L 27/0928 (2013.01); H01L 29/4916 (2013.01); H01L 29/7833 (2013.01);
Abstract
Some demonstrative embodiments include devices and/or systems of a Silicon Controlled Rectifier (SCR). For example, a silicon controlled rectifier (SCR) may include a metal-oxide-semiconductor field-effect transistor (MOSFET), the MOSFET may include a gate; an N-type source region; a non-Lightly Doped Drain (LDD) N-type drain region; and a P-Well region extending between the N-type source region and the non-LDD N-type drain region, and extending between the non-LDD N-type drain region and a drain region of the gate.