The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2018

Filed:

May. 24, 2016
Applicant:

Northrop Grumman Systems Corporation, Falls Church, VA (US);

Inventors:

Stephen J. Sarkozy, Redondo Beach, CA (US);

Yaochung Chen, Rancho Palos Verdes, CA (US);

Richard Lai, Redondo Beach, CA (US);

Assignee:

Northrop Grumman Systems Corporation, Falls Church, VA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 29/06 (2006.01); H01L 29/22 (2006.01); H01L 29/423 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0665 (2013.01); H01L 29/22 (2013.01); H01L 29/401 (2013.01); H01L 29/42356 (2013.01); H01L 29/66522 (2013.01);
Abstract

A field effect transistor (FET) including a substrate, a plurality of semiconductor epitaxial layers deposited on the substrate, and a heavily doped gate layer deposited on the semiconductor layers. The FET also includes a plurality of castellation structures formed on the heavily doped gate layer and being spaced apart from each other, where each castellation structure includes at least one channel layer. A gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer. A voltage potential applied to the gate metal structure modulates the at least one channel layer in each castellation structure from an upper, lower and side direction.


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