Self-latch sense timing in a one-time-programmable memory architecture

Abstract

A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.