The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2018

Filed:

Jan. 20, 2017
Applicant:

Seagate Technology Llc, Cupertino, CA (US);

Inventors:

Young Pil Kim, Eden Prairie, MN (US);

Antoine Khoueir, Edina, MN (US);

Namoh Hwang, Seoul, KR;

Assignee:

SEAGATE TECHNOLOGY LLC, Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G11C 29/50 (2006.01); G11C 29/00 (2006.01); G11C 29/02 (2006.01); G11C 16/34 (2006.01); G11C 29/28 (2006.01); G11C 29/42 (2006.01); G11C 29/26 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 16/3418 (2013.01); G11C 16/3459 (2013.01); G11C 29/00 (2013.01); G11C 29/025 (2013.01); G11C 29/50012 (2013.01); G11C 29/26 (2013.01); G11C 29/28 (2013.01); G11C 29/42 (2013.01); G11C 2029/1204 (2013.01); G11C 2029/5006 (2013.01);
Abstract

Systems and methods for low latency acquisition of soft data from a memory cell based on a sensing time and/or a leakage current are described. In one embodiment, the systems and methods may include applying a first read voltage to a word line of a page of memory cells selected by a processor of a flash memory device for a read operation, applying a pass voltage to word lines associated with one or more different pages of memory cells of the memory block, upon applying the first read voltage sensing whether a bit line of a memory cell in the selected page conducts, measuring a side effect associated with sensing whether the bit line of the memory cell in the selected page conducts, and assigning a LLR value to the memory cell as a soft LDPC input based at least in part on the measured side effect.


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