The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2018

Filed:

Sep. 20, 2006
Applicants:

Toshiharu Hanaoka, Chiba, JP;

Kenichiroh Yamamoto, Chiba, JP;

Hiroyuki Furukawa, Sakura, JP;

Masafumi Ueno, Urayasu, JP;

Yasuhiro Yoshida, Chiba, JP;

Inventors:

Toshiharu Hanaoka, Chiba, JP;

Kenichiroh Yamamoto, Chiba, JP;

Hiroyuki Furukawa, Sakura, JP;

Masafumi Ueno, Urayasu, JP;

Yasuhiro Yoshida, Chiba, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 7/01 (2006.01); G09G 3/20 (2006.01); H04N 5/14 (2006.01); H04N 5/445 (2011.01); H04N 5/45 (2011.01); H04N 21/431 (2011.01); H04N 21/44 (2011.01); H04N 21/4402 (2011.01); H04N 21/443 (2011.01);
U.S. Cl.
CPC ...
G09G 3/20 (2013.01); H04N 5/145 (2013.01); H04N 5/44504 (2013.01); H04N 5/45 (2013.01); H04N 7/013 (2013.01); H04N 21/4316 (2013.01); H04N 21/44008 (2013.01); H04N 21/440281 (2013.01); G09G 2320/106 (2013.01); G09G 2340/0435 (2013.01); G09G 2340/125 (2013.01); H04N 7/014 (2013.01); H04N 21/4435 (2013.01);
Abstract

In an image display device having a frame rate converting (FRC) portion, it is possible to prevent image degradation of a combined image display portion such as an OSD and PinP attributed to the FRC process. The image display device includes: an FRC portionfor converting the number of frames of an input image signal by interpolating an image signal subjected to a motion compensation process between the frames of the input image signal; an OSD processing portionfor superposing an OSD signal on the input image signal, and a controlling portion. The FRC portionhas a motion vector detecting portionfor detecting a motion vector between the frames of the input image signal, an interpolation vector evaluating portionfor allocating interpolation vector between frames based on the motion vector information, and an interpolation frame generating portionfor generating an interpolation frame from the interpolation vector. When the OSD signal is superposed on the input image signal, the controlling portiondisables the motion compensation process of the FRC portionby making the motion vector detected by the motion vector detecting portion0 vector.


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