The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2018

Filed:

Sep. 07, 2016
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Ronan Casey, Cork, IE;

Catherine Hearne, Fermoy, IE;

Jinyung Namkoong, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/05 (2006.01); H03K 5/151 (2006.01); H04L 7/00 (2006.01); H03K 5/06 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/05 (2013.01); H03K 5/06 (2013.01); H03K 5/065 (2013.01); H03K 5/1515 (2013.01); H04L 7/0025 (2013.01); H03K 2005/00052 (2013.01);
Abstract

The phase interpolator comprises a first charge pump configured to receive a first differential clock signal having a first clock phase, wherein the first charge pump has a first current path and a second current path coupled between a first pull-up current source and a first pull-down current source, wherein the first current path comprises a first NMOS steering switch coupled between a first output node and the first pull-down current source and the second current path comprises a second NMOS steering switch coupled between a second output node and the first pull-down current source; and a second charge pump configured to receive a second differential clock signal having a second clock phase, wherein the second charge pump has a third current path and a fourth current path coupled between a second pull-up current source and a second pull-down current source, and wherein the third current path comprises a third NMOS steering switch coupled between the first output node and the second pull-down current source and the fourth current path comprises a fourth NMOS steering switch coupled between the second node and the second pull-down current source.


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