The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2018

Filed:

Dec. 03, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Niladri Narayan Mojumder, San Diego, CA (US);

Stanley Seungchul Song, San Diego, CA (US);

Zhongze Wang, San Diego, CA (US);

Kern Rim, San Diego, CA (US);

Choh Fei Yeap, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01); G11C 5/06 (2006.01); G11C 8/14 (2006.01); G11C 11/418 (2006.01); G11C 11/412 (2006.01); G11C 8/16 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11 (2013.01); G11C 5/063 (2013.01); G11C 8/14 (2013.01); G11C 8/16 (2013.01); G11C 11/412 (2013.01); G11C 11/418 (2013.01); H01L 21/768 (2013.01); H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H01L 27/1104 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells are disclosed. In one aspect, an SRAM bit cell is disclosed employing write wordline in second metal layer, first read wordline in third metal layer, and second read wordline in fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have wider widths, which decrease wordline resistance, decrease access time, and increase performance of SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks inside and outside of a boundary edge of the SRAM bit cell. Landing pads corresponding to the write wordline are placed on corresponding tracks within the boundary edge of the SRAM bit cell.


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