Memory device and a memory device test system

Abstract

A memory device includes a controller, a multiplexer, a deserializer, a data modifier, a memory cell array and an error detector. The controller is configured to generate signals in response to an address signal and a command signal. The multiplexer is configured to output a clock signal as internal data signals when the test mode signal is activated. The deserializer is configured to deserialize N bit values included in the internal data signals to generate deserialized signals. The data modifier is configured to invert the deserialized signals to generate bit line signals in response to an inversion control signal and the data modifying signals. The memory cell array is configured to store the bit line signals to memory cells corresponding to the address signal. The error detector is configured to determine if an error exists in signals read from the memory cells and to output an error detecting signal.