The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2018

Filed:

Mar. 25, 2010
Applicants:

Seong-ook Jung, Seoul, KR;

Hyunkook Park, Seoul, KR;

Seung-chul Song, Austin, TX (US);

Mohamed Hassan Abu-rahma, San Diego, CA (US);

Lixin GE, San Diego, CA (US);

Zhongze Wang, San Diego, CA (US);

Beom-mo Han, San Diego, CA (US);

Inventors:

Seong-Ook Jung, Seoul, KR;

Hyunkook Park, Seoul, KR;

Seung-Chul Song, Austin, TX (US);

Mohamed Hassan Abu-Rahma, San Diego, CA (US);

Lixin Ge, San Diego, CA (US);

Zhongze Wang, San Diego, CA (US);

Beom-Mo Han, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G11C 11/412 (2013.01);
Abstract

A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.


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