The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2018

Filed:

Mar. 09, 2015
Applicant:

Nordic Semiconductor Asa, Trondheim, NO;

Inventors:

Junaid Elahi, Oslo, NO;

Joar Olai Rusten, Trondheim, NO;

Lasse Olsen, Trondheim, NO;

Lars Sundell, Moss, NO;

Assignee:

NORDIC SEMICONDUCTOR ASA, Trondheim, NO;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01); G06F 13/404 (2013.01); G06F 13/4282 (2013.01);
Abstract

Peripherals () are connected to a processor () and a programmable peripheral interconnect () is connected to each peripheral. One of the peripherals () is configured to signal an event to the interconnect, and one of the peripherals () is configured to respond to a task signal from the interconnect by performing a task. The task-receiving peripheral () has a task register (), addressable by the processor (), and performs the task in response to a change in the contents of the register (). The interconnect () accesses a memory () in which a mapping is stored between an event of a first peripheral () and a task of a second peripheral (), the mapping comprising (i) an identification of the event, and (ii) the address of a task register (). The mapping causes the interconnect () to provide a channel by sending a task signal to the second peripheral () in response to a signal of the event from the first peripheral ().


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