The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2018

Filed:

Mar. 14, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Vaishnav Srinivas, San Diego, CA (US);

Bernie Jord Yang, San Diego, CA (US);

Michael Brunolli, Escondido, CA (US);

David Ian West, San Diego, CA (US);

Charles David Paynter, Encinitas, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/66 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 24/17 (2013.01); H01L 22/32 (2013.01); H01L 24/05 (2013.01); H01L 24/14 (2013.01); H01L 24/29 (2013.01); H01L 24/81 (2013.01); H01L 21/563 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/27 (2013.01); H01L 24/30 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 2224/02377 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/0556 (2013.01); H01L 2224/05558 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13028 (2013.01); H01L 2224/13109 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/14165 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/27462 (2013.01); H01L 2224/29028 (2013.01); H01L 2224/29078 (2013.01); H01L 2224/29147 (2013.01); H01L 2224/3012 (2013.01); H01L 2224/3213 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81193 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/831 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/07802 (2013.01); H01L 2924/381 (2013.01);
Abstract

Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.


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