The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2018

Filed:

Aug. 24, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Pooja R. Batra, White Plains, NY (US);

John W. Golz, Manassas, VA (US);

Mark Jacunski, Colchester, VT (US);

Toshiaki Kirihata, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/522 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 24/24 (2013.01); H01L 24/80 (2013.01); H01L 24/92 (2013.01); H01L 24/94 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 24/82 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/24145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/9202 (2013.01); H01L 2224/94 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06558 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01);
Abstract

Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.


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