The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2018

Filed:

Mar. 16, 2017
Applicant:

Hitachi Kokusai Electric Inc., Tokyo, JP;

Inventors:

Teruo Yoshino, Toyama, JP;

Takeshi Yasui, Toyama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/687 (2006.01); H01L 21/67 (2006.01); H01L 21/677 (2006.01); H01L 21/02 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 22/26 (2013.01); H01L 21/02164 (2013.01); H01L 21/67098 (2013.01); H01L 21/67201 (2013.01); H01L 21/67745 (2013.01); H01L 21/6838 (2013.01); H01L 21/68707 (2013.01);
Abstract

The present disclosure provides a technique including a method of manufacturing a semiconductor device, which is capable of improving a processing uniformity of a plurality of substrates. The method may include: (a) subjecting a substrate accommodated in one of a plurality of process chambers to a thermal process: (b) transferring the substrate processed in (a) by a transfer robot provided in a vacuum transfer chamber connected to the plurality of process chambers from the one of a plurality of process chambers to a loadlock chamber connected to the vacuum transfer chamber; and (c) cooling the substrate accommodated in the loadlock chamber by supplying an inert gas to the substrate accommodated in the loadlock chamber according to a cooling recipe.


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