The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2018

Filed:

Feb. 02, 2015
Applicants:

Jong-pil Lee, Suwon-si, KR;

Su-hyun Yun, Seoul, KR;

Jae-seung Choi, Suwon-si, KR;

Jung-hun Heo, Suwon-si, KR;

Inventors:

Jong-Pil Lee, Suwon-si, KR;

Su-Hyun Yun, Seoul, KR;

Jae-Seung Choi, Suwon-si, KR;

Jung-Hun Heo, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/26 (2006.01); G06F 1/32 (2006.01); G06F 13/00 (2006.01); G11C 7/08 (2006.01); G11C 7/10 (2006.01); G11C 11/419 (2006.01); G11C 5/14 (2006.01); G11C 7/04 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3275 (2013.01); G06F 1/324 (2013.01); G11C 7/08 (2013.01); G11C 7/1045 (2013.01); G11C 11/419 (2013.01); G11C 5/14 (2013.01); G11C 7/04 (2013.01); G11C 7/22 (2013.01);
Abstract

An integrated circuit, a method of controlling an operation timing of a memory device, an application processor, and a power manager are provided. The application processor includes: a power manager configured to determine a first operating power level, from among a plurality of operating power levels, to determine a first timing margin corresponding to the first operating power level, to generate a first gray code signal indicating the first timing margin, and to output the first gray code signal; and a first memory device configured to adjust an operation timing according to the first timing margin indicated by the first gray code signal, wherein the power manager is configured to provide the first operating power level to the first memory device.


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