The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2018

Filed:

Aug. 24, 2015
Applicant:

Multek Technologies Ltd., San Jose, CA (US);

Inventors:

Kwan Pen, Guandong, CN;

Pui Yin Yu, Tsuen Wan, HK;

Assignee:

Multek Technologies Limited, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 3/42 (2006.01); H05K 3/46 (2006.01); H05K 3/00 (2006.01); H05K 3/06 (2006.01); H05K 3/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/115 (2013.01); H05K 1/0216 (2013.01); H05K 1/112 (2013.01); H05K 3/0058 (2013.01); H05K 3/06 (2013.01); H05K 3/181 (2013.01); H05K 3/188 (2013.01); H05K 3/42 (2013.01); H05K 3/422 (2013.01); H05K 3/424 (2013.01); H05K 3/429 (2013.01); H05K 3/4623 (2013.01); H05K 3/4638 (2013.01); H05K 1/0298 (2013.01); H05K 3/4602 (2013.01); H05K 2201/095 (2013.01); H05K 2201/09545 (2013.01); H05K 2201/09554 (2013.01); H05K 2201/10303 (2013.01);
Abstract

A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the plug non-conductive layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.


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