The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2018
Filed:
Jun. 17, 2016
Nxp B.v., Eindhoven, NL;
NXP B.V., Eindhoven, NL;
Abstract
There is described a driver circuit () for providing biasing voltages to a flash memory device, the driver circuit comprising (a) a level shifter latch () comprising a first latch input terminal (), a first latch control terminal (), a latch voltage supply terminal (), a first latch output terminal (), and a second latch output terminal (), wherein the level shifter latch () is adapted to provide, in dependency of a voltage at the first latch input terminal (), one of a first voltage and a second voltage at the first latch output terminal () and the other one of the first voltage and the second voltage at the second latch output terminal (), wherein the first voltage is dependent on a voltage applied to the latch voltage supply terminal () and the second voltage is dependent on a voltage applied to the first latch control terminal (), (b) a first output stage () comprising a first switching element (N, N), a second switching element (N), a first voltage supply terminal (), a second voltage supply terminal (), and a first biasing voltage output terminal (), wherein the first switching element (N, N) is adapted to connect the first biasing voltage output terminal () to the first voltage supply terminal () in dependency of the voltage at the first latch output terminal (), and wherein the second switching element (N) is adapted to connect the first biasing voltage output terminal () to the second voltage supply terminal () in dependency of the voltage at the second latch output terminal (), and (c) a second output stage () comprising a third switching element (N), a fourth switching element (N), a third voltage supply terminal (), a fourth voltage supply terminal (), and a second biasing voltage output terminal (), wherein the third switching element (N) is adapted to connect the second biasing voltage output terminal () to the third voltage supply terminal () in dependency of the voltage at the first latch output terminal (), and wherein the fourth switching element (N) is adapted to connect the second biasing voltage output terminal () to the fourth voltage supply terminal () in dependency of the voltage at the second latch output terminal ().There is also described a memory system and a method of operating the driver circuit.