Semiconductor memory device

Abstract

A semiconductor memory device according to an embodiment includes a memory cell array that includes a plurality of memory cells. The memory cell array comprises: a plurality of first conductive layers that are stacked in a first direction above a substrate and extend in a second direction intersecting the first direction; a second conductive layer extending in the first direction; a variable resistance film provided at intersections of the plurality of first conductive layers and the second conductive layer; a first select transistor disposed closer to a side of the substrate than a lowermost layer of the plurality of first conductive layers, the first select transistor including a first select gate line intersecting the second conductive layer; a third conductive layer that extends in a third direction intersecting the second direction and is connected to a lower end of the second conductive layer via the first select transistor; and a second select transistor disposed between at least one pair of the plurality of first conductive layers adjacent in the first direction, the second select transistor including a second select gate line intersecting the second conductive layer.