The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2018
Filed:
Jul. 12, 2016
Method of making a fully depleted semiconductor-on-insulator programmable cell and structure thereof
Applicant:
Avago Technologies General Ip (Singapore) Pte. Ltd., Singapore, SG;
Assignee:
Avago Technologies General IP (Singapore) Pte. Ltd., Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 27/112 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/161 (2006.01); H01L 23/528 (2006.01); H01L 29/51 (2006.01); H01L 21/84 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11206 (2013.01); H01L 21/84 (2013.01); H01L 23/528 (2013.01); H01L 23/5252 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/517 (2013.01);
Abstract
A programmable cell includes a semiconductor-on-insulator substrate, a program gate, and a word line gate. The semiconductor-on-insulator substrate includes a semiconductor layer. The semiconductor layer includes a first doped source/drain region, a second doped source/drain region and a region comprising germanium. The program gate is disposed above the region comprising germanium and includes a first gate dielectric layer disposed below a gate conductor. The word line gate is disposed between the first doped source/drain region and the second doped source/drain region.