The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2018

Filed:

Jul. 12, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Hyuk Kim, Seongnam-si, KR;

Jae-Ho Min, Suwon-si, KR;

Jong-Kyoung Park, Suwon-si, KR;

Seung-Pil Chung, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 27/11573 (2017.01); H01L 27/11582 (2017.01); H01L 27/11575 (2017.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/76816 (2013.01); H01L 21/76829 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01); H01L 27/1157 (2013.01);
Abstract

A vertical memory device includes a plurality of gate lines, at least one etch-stop layer, channels, and contacts. The gate lines are stacked and spaced apart from each other along a first direction with respect to a surface of substrate. Each of the gate lines includes step portion protruding in a second direction. The at least one etch-stop layer covers the step portion of at least one of the gate lines and includes conductive material. The channels extend through the gate lines in the first direction. The contacts extend through the at least one etch-stop layer and are on the step portions of the gate lines.


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