The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2018

Filed:

Nov. 04, 2015
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventors:

Tomokazu Nakashima, Kawasaki, JP;

Masayuki Itoh, Kawasaki, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01G 9/00 (2006.01); H01G 4/30 (2006.01); H01G 4/12 (2006.01); H01G 4/008 (2006.01); H01G 4/018 (2006.01); H01G 4/38 (2006.01); H01G 4/012 (2006.01); H01G 4/232 (2006.01);
U.S. Cl.
CPC ...
H01G 4/30 (2013.01); H01G 4/008 (2013.01); H01G 4/012 (2013.01); H01G 4/018 (2013.01); H01G 4/12 (2013.01); H01G 4/232 (2013.01); H01G 4/385 (2013.01); Y10T 29/417 (2015.01); Y10T 29/435 (2015.01); Y10T 29/49124 (2015.01);
Abstract

A capacitor includes: dielectric layers including a first dielectric layer, a second dielectric layer, and at least one intermediate dielectric layer laminated between the first dielectric layer and the second dielectric layer; first interlayer electrode and second interlayer electrode arranged alternately with each other between at least two layers among the dielectric layers; a first external electrode disposed on lateral surfaces of the dielectric layers and coupled to the first interlayer electrode; and a second external electrode disposed on lateral surfaces of the dielectric layers and coupled to the second interlayer electrode, wherein the intermediate dielectric layer includes first internal electrodes coupled to the first interlayer electrode, arranged in a plane direction of the intermediate dielectric layer and spaced apart from each other, and second internal electrodes coupled to the second interlayer electrode, arranged alternately with the first internal electrodes and spaced apart from the first internal electrodes.


Find Patent Forward Citations

Nakashima, Tomokazu. (2018). Method of manufacturing capacitor including intermediate dielectric layer with first internal electrodes and second internal electrodes (U.S. Patent No. 9865396). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9865396

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…