The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2018

Filed:

Apr. 27, 2016
Applicant:

Invecas, Inc., Santa Clara, CA (US);

Inventors:

Thomas Chadwick, Essex, VT (US);

Kevin W. Gorman, Essex, VT (US);

Nancy Pratt, Essex, VT (US);

Assignee:

Invecas, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/38 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G11C 29/44 (2013.01);
Abstract

A memory diagnostic system comprises a test engine and a miscompare logic. The test engine provides test instructions with expected data to a memory under test ('MUT'). The MUT processes such test patterns and outputs the results of such test patterns as stored data. The miscompare logic has local miscompare logics and a global miscompare logic. Each of the local miscompare logics compares a predefined range of bits of the expected data with a corresponding predefined range of bits of the stored data. One or more miscompare flags are generated for one or more miscompares determined by the local miscompare logics. The global miscompare logic monitors the one or more miscompare flags. When a total number of the miscompare flags exceeds a threshold number, the global miscompare logic generates a pause signal to the local miscompare logics to capture a current state of the local miscompare logics.


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