The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2018

Filed:

Oct. 29, 2014
Applicants:

Forschungszentrum Jülich Gmbh, Jülich, DE;

Rheinisch-westfälische Technische Hochschule, Aachen, DE;

Inventors:

Jan Van Den Hurk, Aachen, DE;

Elke Linn, Wuerselen, DE;

Rainer Waser, Aachen, DE;

Ilia Valov, Aachen, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 13/0011 (2013.01); G11C 13/0069 (2013.01); H01L 45/08 (2013.01); H01L 45/1266 (2013.01); H01L 45/142 (2013.01); H01L 45/143 (2013.01); H01L 45/144 (2013.01); H01L 45/148 (2013.01); G11C 2013/0047 (2013.01); G11C 2013/0052 (2013.01); G11C 2213/33 (2013.01); G11C 2213/52 (2013.01);
Abstract

A method for reading out a resistive memory cell comprising two electrodes that are spaced from each other by an ion-conducting resistive material was developed, the memory cells being transferrable from a stable state having a higher resistance value (high resistive state, HRS) to a stable state having a lower resistance value (low resistive state, LRS) when a write voltage is applied. A read voltage is applied as a read pulse for reading out, wherein the number of ions driven through the ion-conducting resistive material during the pulse is set by way of the level and duration of the pulse in such a way, proceeding from the HRS state, they suffice for forming an electrically conducting path through the ion-conducting resistive material at least until the onset of a flow of current through this path, and thus for the transition into a metastable VRS state (volatile resistance state) having a reduced resistance value and a predefined relaxation time for return into the HRS state, but not for transition into the LRS state. In this way, it is ensured that, in all cases, the memory cell once is again in the same state after the read-out as it was prior to the read-out. This allows in particular memory elements that are composed of an antiserial circuit composed of two memory cells to be read out non-destructively, without this diminishing the option of implementing large arrays composed of these memory elements.


Find Patent Forward Citations

Loading…