The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9865316 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 09, 2018

Filed:

Jan. 21, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Sharad Kumar Gupta, Bangalore, IN;

Mukund Narasimhan, Bangalore, IN;

Veerabhadra Rao Boda, East Godavari, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/22 (2006.01); G11C 11/419 (2006.01); G11C 11/418 (2006.01); G11C 7/12 (2006.01); G11C 8/08 (2006.01); G11C 8/10 (2006.01); G11C 8/18 (2006.01);
U.S. Cl.
CPC ...
G11C 7/227 (2013.01); G11C 7/12 (2013.01); G11C 7/22 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); G11C 8/18 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); G11C 2207/229 (2013.01);
Abstract

A memory is provided in which the word line assertion during a write operation is delayed until the discharge of a dummy bit line is detected.


Find Patent Forward Citations

Gupta, Sharad. (2018). Memory with a word line assertion delayed by a bit line discharge for write operations with improved write time and reduced write power (U.S. Patent No. 9865316). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9865316

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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