The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2018

Filed:

Feb. 24, 2012
Applicants:

Allan Cantle, Westlake Village, CA (US);

Patrick Weber, Oxnard, CA (US);

Mark Gilliam, Thousand Oaks, CA (US);

Prashant Joshi, Thousand Oaks, CA (US);

Inventors:

Allan Cantle, Westlake Village, CA (US);

Patrick Weber, Oxnard, CA (US);

Mark Gilliam, Thousand Oaks, CA (US);

Prashant Joshi, Thousand Oaks, CA (US);

Assignee:

INTERCONNECT SYSTEMS, INC., Camarillo, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/14 (2006.01); G11C 5/04 (2006.01); H05K 3/34 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
G11C 5/04 (2013.01); H05K 1/141 (2013.01); H05K 1/144 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 2924/0002 (2013.01); H05K 3/3436 (2013.01); H05K 2201/042 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/2036 (2013.01);
Abstract

Solid state memory modules are disclosed having increased density for module size/footprint. Different embodiments also provide for improved interconnect arrangements between the memory modules and the corresponding field programmable gate array (FPGA), micro-processor (μP), or application-specific integrated circuit (ASIC). These interconnects provide for greater module interconnect flexibility, operating speed and operating efficiency. Some memory module embodiments according to the present invention comprises a plurality of solid state memory devices arranged on a first printed circuit board. A second printed circuit board is on and electrically connected to the first printed circuit board, with the second printed circuit board having a pin-out for direct coupling to a host device.


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