The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2018

Filed:

Nov. 03, 2015
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Mrinal J. Sarmah, Hyderabad, IN;

Bokka Abhiram Sai Krishna, Hyderabad, IN;

Anil Kumar A V, Hyderabad, IN;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); G06F 15/177 (2006.01); G06F 9/44 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4408 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01);
Abstract

An integrated circuit (IC) that includes a processor circuit can be booted by receiving, using a storage interface circuit of the IC, a first boot image from a nonvolatile memory chip. The first boot image is executed on a processor circuit of the IC to configure a bus interface module that is designed to communicate with a host device over a communication bus that links multiple devices and the IC. Using the bus interface module, a second boot image is received from the memory of the host device to a memory of the IC. The IC is booted by executing the second boot image.


Find Patent Forward Citations

Quick Actions:

Sarmah, Mrinal. (2018). Multistage boot image loading by configuration of a bus interface (U.S. Patent No. 9864605). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9864605

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