The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2018
Filed:
Jun. 24, 2016
Qualcomm Incorporated, San Diego, CA (US);
Dorav Kumar, San Diego, CA (US);
Venkatasubramanian Narayanan, San Diego, CA (US);
Bala Krishna Thalla, San Diego, CA (US);
Seid Hadi Rasouli, San Diego, CA (US);
Radhika Vinayak Guttal, San Diego, CA (US);
Sivakumar Paturi, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
A MOS device may include a first logic component with a first input located on a second track and a first output located on the third track. The MOS device may include a second logic component with a second input located on the fourth track and a second output located on a fifth track. For example, the MOS device includes a first interconnect on a Mlayer that is coupled to the first input on the second track. In another example, the MOS device includes a second interconnect on the Mlayer that is coupled to the first output on the third track. The MOS device includes a third interconnect on a Mlayer that is coupled to the second input on the fourth track. Still further, the MOS device includes a fourth interconnect on the Mlayer that is coupled to the second output on the fifth track.