The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2018

Filed:

Jan. 24, 2017
Applicant:

Electronics and Telecommunications Research Institute, Daejeon, KR;

Inventors:

Woojoo Lee, Daejeon, KR;

Young-Su Kwon, Daejeon, KR;

Kyung Jin Byun, Daejeon, KR;

Jin Ho Han, Seoul, KR;

Nak Woong Eum, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); G06F 3/02 (2006.01); H01L 27/11 (2006.01); H03K 19/0944 (2006.01); H03K 17/96 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0013 (2013.01); G06F 3/0202 (2013.01); H01L 27/1104 (2013.01); H01L 29/49 (2013.01); H03K 17/9638 (2013.01); H03K 19/0944 (2013.01);
Abstract

An Ultra Low Voltage (ULV) digital circuit includes a logic circuit comprising a plurality of logic gates and a plurality of buffered interconnects for connecting between the plurality of logic gates, a temperature sensor configured to detect a temperature of the logic circuit, and a voltage controller configured to control a driving voltage provided to the logic circuit in order to reduce a power consumption of the logic circuit based on the detected temperature. Each of the plurality of logic gates and buffered interconnects reduces a signal delay as a temperature increases.


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