The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2018

Filed:

Apr. 21, 2017
Applicant:

Skyworks Solutions, Inc., Woburn, MA (US);

Inventor:

Daniel Lee Kaczman, Newbury Park, CA (US);

Assignee:

SKYWORKS SOLUTIONS, INC., Woburn, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/38 (2015.01); H03F 1/56 (2006.01); H04B 1/40 (2015.01); H03F 3/19 (2006.01); H03F 3/24 (2006.01);
U.S. Cl.
CPC ...
H03F 1/565 (2013.01); H03F 3/19 (2013.01); H03F 3/245 (2013.01); H04B 1/40 (2013.01); H03F 2200/102 (2013.01); H03F 2200/387 (2013.01); H03F 2200/391 (2013.01); H03F 2200/451 (2013.01);
Abstract

Apparatus and methods for output matching of power amplifiers are provided. In certain configurations, a mobile device includes a power amplifier that amplifies an RF signal to generate an amplified RF signal at an output, an envelope tracker that generates a power amplifier supply voltage based on an envelope of the RF signal, a supply voltage biasing circuit that provides the power amplifier supply voltage from the envelope tracker to the output of the power amplifier, and an output matching circuit connected to the output of the power amplifier via an input node. The output matching circuit includes a first capacitor and a first inductor connected in series between the input node and ground, a second capacitor connected between the input node and ground, a second inductor connected between the input node and an intermediate node, and a DC blocking capacitor connected between the intermediate node and an output node.


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