The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2018

Filed:

Sep. 02, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Heungkyu Kwon, Seongnam-si, KR;

Inhyuk Kim, Hanam-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/66 (2006.01); G06F 21/30 (2013.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); G06F 21/30 (2013.01); H01L 22/32 (2013.01); H01L 24/03 (2013.01); H01L 24/11 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/85 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 25/0657 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/0237 (2013.01); H01L 2224/0392 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05024 (2013.01); H01L 2224/06515 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06558 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18162 (2013.01);
Abstract

A chip includes a core layer, at least one redistribution layer formed on the core layer, and at least one triple pad connected to a pad of the core layer through the at least one redistribution layer or at least one via connected to the at least one redistribution layer. The at least one triple pad includes a bonding pad, a redistribution layer pad connected to the at least one redistribution layer, and a test pad configured to perform a wafer level test. The bonding pad, the redistribution layer pad and the test pad are connected to one another through the at least one redistribution layer, and the test pad is disposed in a core area that overlaps the core layer.


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