The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2018

Filed:

May. 27, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Hyun-joong Kim, Gyeonggi-do, KR;

Soo-hyeong Kim, Gyeonggi-do, KR;

Sang-hoon Shin, Gyeonggi-do, KR;

Ju-yun Jung, Gyeonggi-do, KR;

Ho-young Song, Gyeonggi-do, KR;

Kyo-min Sohn, Gyeonggi-do, KR;

Hae-suk Lee, Gyeonggi-do, KR;

Bu-il Jung, Gyeonggi-do, KR;

Han-vit Jeong, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G11C 29/52 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/52 (2013.01); G06F 11/1048 (2013.01); G11C 2029/0411 (2013.01);
Abstract

A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.


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