The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2018

Filed:

Aug. 26, 2014
Applicant:

Sharp Kabushiki Kaisha, Osaka-shi, Osaka, JP;

Inventors:

Sumio Katoh, Osaka, JP;

Naoki Ueda, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 17/18 (2006.01); G11C 13/00 (2006.01); G11C 17/16 (2006.01); G11C 19/28 (2006.01); H01L 27/105 (2006.01); H01L 27/112 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01); G02F 1/1345 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
G11C 17/18 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); G11C 17/16 (2013.01); G11C 17/165 (2013.01); G11C 19/28 (2013.01); H01L 27/1052 (2013.01); H01L 27/11206 (2013.01); H01L 29/24 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); G02F 1/1368 (2013.01); G02F 1/13452 (2013.01); G02F 2201/123 (2013.01); G11C 2213/53 (2013.01);
Abstract

A semiconductor device () includes: a memory cell; and a writing control circuit (), wherein the memory cell includes a memory transistor (A) which has an active layer (A), the active layer (A) including a metal oxide, the memory transistor (A) is a transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Ids depends on a gate-source voltage Vgs to a resistor state where the drain current Ids does not depend on the gate-source voltage Vgs, and the writing control circuit () is configured to control voltages applied to a drain electrode, a source electrode and a gate electrode such that Vgs≧Vds+Vth is satisfied where Vth is a threshold voltage of the memory transistor (A) and Vds is a drain-source voltage of the memory transistor (A), whereby writing in the memory transistor (A) is performed.


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