The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2018
Filed:
Jul. 27, 2016
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Han-gi Jung, Suwon-si, KR;
Young-kwon Jo, Suwon-si, KR;
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4093 (2006.01); G11C 11/408 (2006.01); G11C 11/4096 (2006.01); G11C 11/4076 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4093 (2013.01); G11C 7/227 (2013.01); G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); G11C 2207/229 (2013.01); G11C 2207/2272 (2013.01);
Abstract
A memory device may include a latency control circuit configured to control a write latency and a read latency. The memory device compensates a write latency corresponding to a write command in response to a clock signal for a delay time on a data input path, and generates a write latency control signal. Write data input to a data bus in response to the write latency control signal is immediately aligned with the clock signal and latched and provided to a memory cell array.