logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9858220 B1

PDFFull Text
Date of Patent:
Jan. 02, 2018

Filed:

Mar. 17, 2015

Computing architecture with concurrent programmable data co-processor

Applicant:

Purdue Research Foundation, West Lafayette, IN (US);

Inventors:

Eugenio Culurciello, Lafayette, IN (US);

Berin Eduard Martini, Lafayette, IN (US);

Vinayak Anand Gokhale, West Lafayette, IN (US);

Jonghoon Jin, West Lafayette, IN (US);

Aysegul Dundar, Lafayette, IN (US);

Assignee:

Purdue Research Foundation, West Lafayette, IN (US);

Attorney:

Purdue Research Foundation

Primary Examiner:

Raymond Phan

Int. Cl.
CPC ...
G06F 13/20 (2006.01); G06F 13/28 (2006.01); G06F 12/02 (2006.01); G06F 9/44 (2006.01); G06F 9/46 (2006.01); G06N 3/063 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 9/4411 (2013.01); G06F 9/46 (2013.01); G06F 12/023 (2013.01); G06N 3/063 (2013.01); G06F 2212/261 (2013.01); Y02B 60/1228 (2013.01);
Abstract

A coprocessor (PL) is disclosed. The PL includes a memory router, at least one collection block that is configured to transfer data to/from the memory router, each collection block includes a collection router that is configured to i) transfer data to/from the memory router, ii) transfer data to/from at least one collection router of a neighboring collection block, and iii) transfer data to/from blocks within the collection block, and at least one programmable operator that is configured to i) transfer data to/from the collection router, and ii) perform a programmable operation on data received from the collection router.

Find Patent Forward Citations

Culurciello, Eugenio. (2018). Computing architecture with concurrent programmable data co-processor (U.S. Patent No. 9858220). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9858220

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…