The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2018
Filed:
Feb. 20, 2015
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Christopher Edward Koob, Round Rock, TX (US);
Erich James Plondke, Austin, TX (US);
Jiajin Tu, Shanghai, CN;
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 12/1027 (2016.01); G06F 11/07 (2006.01); G06F 12/08 (2016.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1027 (2013.01); G06F 1/32 (2013.01); G06F 11/073 (2013.01); G06F 11/079 (2013.01); G06F 12/08 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/502 (2013.01); G06F 2212/684 (2013.01); Y02B 60/1225 (2013.01);
Abstract
A translation lookaside buffer (TLB) stores translation entries. The translation entries include a virtual address, a physical address and a memory local/not-local flag. When a processor is in a low power/local memory mode a virtual address is received. A matching translation entry has a local/not-local flag. Upon the local/not-local flag indicating the physical address of the matching translation entry being outside the local memory, an out-of-access-range memory access exception is generated.