The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2018

Filed:

Jun. 18, 2014
Applicant:

Empire Technology Development Llc, Wilmington, DE (US);

Inventor:

Yan Solihin, Raleigh, NC (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 12/08 (2016.01); G06F 1/32 (2006.01); G06F 15/80 (2006.01); G11C 11/16 (2006.01); G06F 12/0842 (2016.01);
U.S. Cl.
CPC ...
G06F 9/466 (2013.01); G06F 1/3275 (2013.01); G06F 12/0842 (2013.01); G06F 15/80 (2013.01); G11C 11/161 (2013.01); G06F 2212/283 (2013.01); Y02B 60/1225 (2013.01); Y02B 60/1228 (2013.01);
Abstract

Technologies are generally described for systems, devices and methods relating to multicore processors. The multicore processors may include first and second tiles with first and second caches, respectively. The first cache may include first magnetoresistive random access memory (MRAM) cells with first storage characteristics. The second cache may include second MRAM cells with second storage characteristics different from the first storage characteristics. In some examples, an interconnect structure may be coupled to the first and second tiles and may be configured to provide communication between the first tile and the second tile. Methods for handling migration between tiles and cores are also described.


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