The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2017

Filed:

Oct. 18, 2016
Applicant:

Realtek Semiconductor Corporation, Hsinchu, TW;

Inventors:

Kai-Yi Huang, Taipei, TW;

Sheng-Hung Lin, New Taipei, TW;

Yuh-Sheng Jean, Hsinchu County, TW;

Ta-Hsun Yeh, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/93 (2006.01); H01L 29/94 (2006.01); H01L 29/08 (2006.01); H01L 49/02 (2006.01); H01L 29/10 (2006.01); H01L 23/535 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/94 (2013.01); H01L 23/535 (2013.01); H01L 27/0629 (2013.01); H01L 28/10 (2013.01); H01L 28/60 (2013.01); H01L 28/91 (2013.01); H01L 29/0843 (2013.01); H01L 29/107 (2013.01); H01L 29/93 (2013.01);
Abstract

A stacked capacitor structure includes a MOS varactor and a stacked capacitor. The stacked capacitor is electrically connected to the MOS varactor. The MOS varactor includes a substrate, a gate, a first source/drain and a second source/drain. The substrate has a well, and the gate is positioned over the well. The first source/drain and the second source/drain are formed in the well and positioned at opposing sides of the gate. The stacked capacitor includes a plurality of metal layers. The metal layers are spaced from each other, stacked above the gate, and positioned below an inductive element.


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