The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2017

Filed:

Jun. 06, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Kyung In Choi, Seoul, KR;

Bon Young Koo, Suwon-si, KR;

Hyun Gi Hong, Seongnam-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 21/3115 (2006.01); H01L 21/311 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 21/768 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41791 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/31155 (2013.01); H01L 21/76825 (2013.01); H01L 21/76897 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes forming active fins on a substrate; forming source/drain regions on the active fins on both sides of a gate structure, the gate structure extending in a direction intersecting with a direction in which the active fins extend; forming an etch stop layer on the source/drain regions; forming an interlayer dielectric layer on the etch stop layer; forming a first opening by partially removing the interlayer dielectric layer so as not to expose the etch stop layer; forming an impurity region within the interlayer dielectric layer by implanting a first impurity ion through the first opening; forming a second opening by removing the impurity region so as to expose the etch stop layer; implanting a second impurity ion into the exposed etch stop layer; and removing the exposed etch stop layer.


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