The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2017

Filed:

Jan. 20, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventor:

Yuji Setta, Kuwana, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11519 (2017.01); H01L 27/11521 (2017.01); H01L 27/11526 (2017.01); H01L 27/11556 (2017.01); H01L 27/11565 (2017.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 27/11519 (2013.01); H01L 27/11521 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01);
Abstract

According to one embodiment, the circuit portion includes a transistor provided at a region separated from the first stacked portion in the substrate. The second stacked portion is provided above the circuit portion. The second stacked portion includes a plurality of first layers and a plurality of second layers. The first layers and the second layers include a first layer and a second layer stacked alternately. An insulating layer is provided above the circuit portion and provided above the substrate between the first stacked portion and the second stacked portion. A height of an uppermost first layer of the second stacked portion from a surface of the substrate is substantially equal to a height of an uppermost electrode layer of the first stacked portion from the surface of the substrate, or is higher than the height of the uppermost electrode layer.


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