The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2017

Filed:

Sep. 21, 2016
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Tomoya Kawai, Kawasaki, JP;

Tsutomu Tezuka, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/72 (2006.01); H01L 29/788 (2006.01); H01L 27/115 (2017.01); H01L 21/28 (2006.01); H01L 27/1157 (2017.01); H01L 27/11565 (2017.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); H01L 27/11565 (2013.01);
Abstract

A semiconductor memory device according to an embodiment includes: a semiconductor substrate; a plurality of first insulating layers and first conductive layers stacked alternately in a first direction above the semiconductor substrate; a first semiconductor layer extending in the first direction; and a memory layer disposed between one of the first insulating layers and the first semiconductor layer and between one of the first conductive layers and the first semiconductor layer, the memory layer including a charge accumulation layer, the first semiconductor layer and the memory layer having a gap, between one of the first insulating layers and the first semiconductor layer, and the first semiconductor layer and the memory layer being contacted each other, between one of the first conductive layers and the first semiconductor layer.


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