The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2017

Filed:

Oct. 28, 2016
Applicant:

Mie Fujitsu Semiconductor Limited, Kuwana, MIE, JP;

Inventors:

Lawrence T. Clark, Phoenix, AZ (US);

David A. Kidd, San Jose, CA (US);

Augustine Kuo, Berkeley, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/06 (2006.01); H01L 27/02 (2006.01); G11C 5/14 (2006.01); H03K 3/012 (2006.01); G06F 17/50 (2006.01); G05F 3/20 (2006.01); H01L 27/092 (2006.01); G11C 5/02 (2006.01); H02M 3/07 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0222 (2013.01); G05F 3/205 (2013.01); G06F 17/5045 (2013.01); G11C 5/025 (2013.01); G11C 5/146 (2013.01); G11C 5/147 (2013.01); G11C 5/148 (2013.01); H01L 27/0928 (2013.01); H03K 3/012 (2013.01); H03K 17/063 (2013.01); H02M 2003/076 (2013.01); H02M 2003/078 (2013.01); H03K 2217/0018 (2013.01);
Abstract

A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.


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