The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2017

Filed:

Mar. 10, 2015
Applicant:

Fuji Electric Co., Ltd., Kawasaki-shi, JP;

Inventor:

Norihiro Nashida, Nagano, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-Shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/16 (2006.01); H01L 23/31 (2006.01); H01L 25/16 (2006.01); H01L 23/10 (2006.01); H01L 23/495 (2006.01); H01L 23/373 (2006.01); H01L 23/433 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49811 (2013.01); H01L 23/10 (2013.01); H01L 23/16 (2013.01); H01L 23/3121 (2013.01); H01L 23/3135 (2013.01); H01L 23/3735 (2013.01); H01L 23/4334 (2013.01); H01L 23/49506 (2013.01); H01L 23/49575 (2013.01); H01L 23/49833 (2013.01); H01L 25/162 (2013.01); H01L 2224/48091 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01);
Abstract

The semiconductor device includes an insulating substrate on which is mounted a main circuit part including a semiconductor chip, a printed substrate wherein a conductive connection member connected to the semiconductor chip is disposed on the surface opposing the insulating substrate, a first sealing member that seals so as to enclose the semiconductor chip between the opposing surfaces of the insulating substrate and printed substrate, and a second sealing member that covers the whole excepting a bottom portion of the insulating substrate, the semiconductor device having sealing region regulation rod portions disposed in an outer peripheral portion of a sealing region of the first sealing member and connected between the insulating substrate and printed substrate, wherein the heat resistance temperature of the first sealing member is set to be higher than the heat resistance temperature of the second sealing member.


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