The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2017

Filed:

Jun. 16, 2016
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Claire Fenouillet-Beranger, Voiron, FR;

Philippe Coronel, Barraux, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 27/06 (2006.01); H01L 21/768 (2006.01); H01L 21/822 (2006.01); H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8221 (2013.01); H01L 21/76816 (2013.01); H01L 21/76895 (2013.01); H01L 21/823412 (2013.01); H01L 21/823475 (2013.01); H01L 23/5283 (2013.01); H01L 23/535 (2013.01); H01L 27/0207 (2013.01); H01L 27/0688 (2013.01); H01L 27/088 (2013.01);
Abstract

Integrated circuit equipped with at least two levels of superimposed transistors, comprising: a first transistor at a first level, a first plug, a second plug and a third plug, connected to a drain region, a gate and a source region respectively of the first transistor, the first plug, the second plug and the third plug passing through an insulating layer covering the first transistor a second transistor equipped with an active zone defined in a semi-conducting layer arranged at one end of the plugs and facing the first transistor, the transistor comprising a gate arranged between the first plug and the third plug.


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