The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2017

Filed:

Oct. 21, 2015
Applicant:

Nec Europe Ltd., Heidelberg, DE;

Inventor:

Sebastian Gajek, Flensburg, DE;

Assignee:

NEC CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); G06F 21/62 (2013.01); G06F 21/60 (2013.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 21/6218 (2013.01); G06F 3/0604 (2013.01); G06F 3/0623 (2013.01); G06F 3/0652 (2013.01); G06F 3/0683 (2013.01); G06F 21/602 (2013.01); G06F 2221/2103 (2013.01); G06F 2221/2143 (2013.01);
Abstract

A method for provably secure erasure of data, performed in a memory available to one or more computing devices, includes generating prover state information (PSI), verifier state information (VSI), and common reference information (CRI) based on security information, a pregiven time-constraint, and a pregiven space-constraint, the generating PSI, VSI, and CRI being performed interactively between a prover computing device (PCD), and a verifier computing device, (VCD); computing, by the VCD based on the VSI, a challenge; computing a proof-of-erasure (POE) by the PCD based on the PSI and the computed challenge, the POE having a size corresponding to the pregiven space-constraint; and verifying by the VCD based on the VSI and the POE.


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