Hazard checking control within interconnect circuitry

Abstract

A system-on-check integrated circuitincludes interconnect circuitryconnecting a plurality of transaction sources to a plurality of transaction destinations. The interconnect circuitryincludes a reorder buffer for buffering access transactions and hazard checking circuitryfor performing hazard checks, such as point-of-serialization checks and identifier reuse checks. Check suppression circuitryserves to suppress one or more hazard checks depending upon one or more state variables that themselves depend upon access transactions other than the access transaction for which the hazard checking is or is not to be suppressed. As an example, hazard checking may be suppressed if it is known that there are no other access transactions currently buffered within the reorder bufferor alternatively no other access transactions from the same transaction source buffered within the reorder buffer