The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2017

Filed:

Mar. 31, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

David Paul Hoff, Raleigh, NC (US);

Milind Ram Kulkarni, Raleigh, NC (US);

Benjamin John Bowers, Cary, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 12/0879 (2016.01); G06F 12/0895 (2016.01); G06F 1/06 (2006.01); G06F 12/14 (2006.01); G06F 12/1027 (2016.01);
U.S. Cl.
CPC ...
G06F 12/10 (2013.01); G06F 1/06 (2013.01); G06F 12/0879 (2013.01); G06F 12/0895 (2013.01); G06F 12/1027 (2013.01); G06F 12/1441 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1041 (2013.01); G06F 2212/65 (2013.01);
Abstract

Efficiently generating selection masks for row selections within indexed address spaces is disclosed. In this regard, in one aspect, an indexed array circuit is provided, comprising a start indicator that indicates a start indexed array row of a row selection, and an end indicator that indicates an end indexed array row of the row selection. The indexed array circuit further comprises a plurality of indexed array rows ordered in a logical sequence, each comprising a row-level compare circuit. Each row-level compare circuit is configured to generate a selection mask indicator based on a first parallel comparison of subsets of bits of a logical address of the indexed array row with corresponding subsets of bits of the start indicator, and a second parallel comparison of subsets of bits of the logical address of the indexed array row with corresponding subsets of bits of the end indicator.


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